1. Field of the Invention
This invention relates to memory management software in a software system in a computer for the purpose of testing the software system's operability with the computer. More particularly, the invention relates to diagnosing cache management problems in a kernel of an operating system over a spectrum of selected workloads.
2. Description of Prior Art
In modern computers extensive use is made of cached memory in order to improve system performance. Exemplary memory architecture employs a Harvard cache and a Van Neuman memory. The Harvard designation applies to any memory management architecture in which instructions are stored separately from data. The Van Neuman designation applies to memory management architectures in which data and instructions are stored with data.
The memory provides what is known as virtual memory, when the effective range of addressable memory locations provided to a process is independent of the size of main memory. Most virtual memory schemes are hardware based. In these schemes the virtual address base is divided into fixed sized units termed pages. Virtual memory references are resolved to a page in main memory and an offset within that page.
There are several advantages to the use of virtual memory on computers capable of supporting this facility. Virtual memory allows large programs to be run on machines with main memory configurations that are smaller than the program size. As the program runs, additional sections of its program and data spaces are paged in to memory on demand.
A modern computer system environment with multiple caches for instructions, data and virtual memory mappings is susceptible to cache synchronization problems. There are two causes of cache synchronization error: inconsistencies between cache entries or between split caches, a.k.a. "aliasing"; and inconsistencies between physical memory management and cache memory management. These problems are difficult to detect.
Problems arise in instruction and data caches with a phenomenon known as address aliasing. In virtual memory systems the same physical address can be mapped to two or more completely different logical addresses. Aliasing occurs if both these logical addresses happen to be cached and a write cycle has occurred to one of them. The cache would update one cached copy of the physical address as well as the main memory itself but the cache copy of the other logical address would remain unchanged and would subsequently contain erroneous data.
Another instance of aliasing error can occur when a Harvard/split cache is being used. If for example the instruction cache and memory contained, for a given address, an old instruction, while the data cache contains an updated instruction, the caches would be out of synch. If the next memory access was directed to the same address, the instruction that would be uploaded would be the old, erroneous instruction.
The translation look-aside buffer (TLB) can also be out of synch with a page table entry. This can occur in one of two ways. An entry in the TLB may map to a page table entry for which there is no physical memory allocated. This can occur when there has been a context change and the TLB has not been flushed. Alternately, the TLB may contain physical page allocations that do not coincide with those in the page table. When this occurs the TLB is out of synch with the page table.
What is needed is a way to detect these problems when they occur.